- Extended workshop (2days) on "challenges for three-dimensional (3D) Integrated Circuits and Systems", More info

- Short workshop (in conjunction with ESREF) on "Failure analysis mechanisms in Analog, Power and RF devices and applications" has been held on October 5, More info

Challenges for three-dimensional (3D) Integrated Circuits and Systems

3D integration is a key new trend for microelectronics. At system level, it allows incredible heterogeneous System in Packages with sensors, power, analog, digital and wireless possibilities. For Integrated Circuit manufacturer, the third dimension gives opportunities to stack dies by using 3D interconnections with Through Silicon Vias. In order to fully benefit from these new technologies challenges have to be overcome. It comprises:

- Design (including design for test, design for manufacturing, design for reliability, design for failure analysis),

- Manufacturing,

- Electrical test,

- Reliability test

- Characterization and Reliability challenges

- Failure analysis.

The aim of this workshop is to mix skills coming from involved industries. Contributions on all these topics are welcome. A specific focus will be on characterization and analysis:

- Sample preparation (chip access, repackaging, cross sectioning, ...)

- Acoustic microscopy

- Xray (2D, Computed Tomography)

- Magnetic Microscopy

- Time Domain Reflectometry

- Thermal measurements, hot spot localization

- Terahertz imaging

- Holography, 3D optical

- High resolution electron and ion microscopy (SEM, TEM, HIM, TOFSIMS)

- Thermo mechanical simulation and measurements

Workshop cluster more than 100 attendees; lunches and coffee break were sponsored by CNES CCT MCE. A buffet / cocktail party was held on Monday evening.

Many thanks to our buffet sponsors, please visit their website:  

You can download the presentations at the 3D workshop pages

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Failure analysis mechanisms in Analog, Power and RF devices and applications

In spite of late in the day, near 40 people attended this workshop that was held at ESREF 2011 on October 5. The topic of this EUFANET workshop is "Failure analysis mechanisms in Analog, Power and RF devices and applications"

In many cases, classical failure localization methods, which are common in CMOS devices, don't work on analog, power and some RF devices. Either analog circuitry shows misleading emission signals, thick and closed metallization layers of power semiconductors don't give access to optically-based FA-localization methods, while the backside is not accessible due to high-dose-implants - or equipment limitations considering high frequency applications or high voltage in case of power semiconductors - the challenges in failure localization of such devices are manifold and often unusual.

The following technical presentations have been shown:

•Eric Pieraerts, PRESTO Engineering, “Advanced FA challenges in non-digital products”

•Yann Weber, Olivier Crepel, FREESCALE, “trapped charges phenomena FA case study in mixed-mode device”

•Frank Siegelin, INFINEON, “Backside Analysis Flow for Power Devices”

•Peter Jacob, EMPA, “Mechanical vibration resonance measurements and concerns for plastic encapsulated control modules and power modules in traction applications”

•Andreas Rummel, KLEINDIEK, “High voltage EBIC analysis of an operational amplifier”

•Luc Saury, ST-ERICSSON, “Real-time parametric variation mapping: proof of concept, improvements and application to new parameters”

•Peter Jacob, EMPA, “A new roadmap for the analysis of power semiconductors”

You can also download the Call for Contributition and workshop introduction

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