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2 workshops held in
2012:
- Extended workshop (2days) on “Smart Failure Analysis for New Materials in Electronic Devices” More info - Short workshop (in conjunction with ESREF) (www.esref.org) on "Finding the open: from IC to assembly" More info
Smart Failure Analysis for New Materials in Electronic Devices |
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While most advanced semiconductor companies have reached the 28nm CMOS technology node in manufacturing recently, their leading edge products in conjunction with 3D chip integration, advanced packaging and organic based electronics are entering the consumer market. The introduction of new materials into these products is one of the foremost drivers to enable new functionalities and advantages. In order to support this, analytical techniques for process and materials characterization and failure analysis are challenged to cope with shrinking feature sizes, new failure and degradation modes. In an increasing number of cases, thin films and structures have to be studied on the atomic scale. Techniques like TEM, 3D Atom Probe and AFM-based methods are essential to find root causes of degradation and failure and consequently to ensure quality and product reliability. But also the conventional imaging, preparation and microsurgery techniques need to be kept up-to-date to allow conclusive investigations. The workshop was aimed to offer an opportunity for exchanging ideas, sharing experiences, meeting experts who are involved in R&D of analytical tools at the supplier and the user site. It especially addressed todays and future challenges to failure analysis in a large variety of products/applications ranging from silicon-based to organic and advanced carbon-based electronics. Perspectives on upcoming developments have also been discussed, like: · Overview on new devices concepts: transistors, memories, sensors, etc. and their manufacturing aspects · Advanced or “exotic” materials either within the classical silicon-based technologies or as standalone product (organics, carbon-based) · Preparation for failure analysis for the above mentioned · Failure analysis cases – which FA methods address which FA cases · Imaging techniques: optical-, ion- and electron-beam based, scanning probe … · Material characterization: elemental, structural, chemical analysis · Reliability and characterization challenges, paradigm changes due to new materials · State of the art for ESD, limits and solutions. The presentations of this 2 days workshop were: 1 - Trend & Challenges
2 - FA for organics
3 - FA for Si-based devices 4 - Analysis flows
13th EUFANET Workshop @ ESREF 2012 This EUFANET workshop was held in conjunction with ESREF 2012 at Cagliari (Sardinia, Italy) on "Finding the open: from IC to assembly" topic Failure analysts have a very wide range of techniques to localize defects. Shorts and leakages defect localization at IC levels are often resolved by the use of liquid Crystal, emission microscopy or laser stimulation. Thermography and magnetic microscopy and other techniques expand the ability to localize short circuits even at package and assembly level without direct optical access to the defect. Localizing open circuit is more challenging and only few techniques have been shown to localize open failures at die level, package level and assembly level. LIVA (Light Induced Voltage Alteration), Passive Voltage Contrast, EBAC Emission microscopy on devices running at high frequency or Laser Voltage Imaging have been used for true open at die level. RIL (Resistive Interconnection Localization), SDL (Soft Defect Localization) and other techniques have been applied for open resistive or runnel open at IC level. At pack-age and assembly level Magnetic Microscopy and Lock-in-thermography have also been used to localize resistive open. Time Domain Reflectometry is also well known to detect any kind of defect (from short to open) inducing an impedance change at defect site but it is challenged by spatial resolution. New techniques based on TeraHertz wave or on Magnetic Microscopy (Space Domain Reflectometry) can also target the open defect localization challenge. The purpose of this short workshop has been to share experience on tools and techniques used to localize these open at die level, package level and assembly level. workshop presentayions are:
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